As shown in FIGS. 1(a) and 1(b), most complex state-of-the-art electronic structures such as described above are manufactured by mounting individual components 100 on printed circuit boards 110, sometimes simply referred to as PCB=s (or cards). The components are interconnected on the PCB's to accomplish various desired functions. These are also appropriately connected to edge connectors 120 by means of which the individual PCB's can be plugged into mating connectors of a backplane (or mother board) 130, thus forming, when assembled, a complete electronic system. Those skilled in the art know how to partition the various subfunctions of an electronic system onto various individual PCB's. In a typical example, the memory of a computer processor which would be implemented on a first PCB 110, can also be partially contained on a separate PCB 140, and would possibly be expanded by plugging additional memory boards, such as 150, into extra slots 160 that have been made available in backplane 130. Although the above technique of plugging a plurality of spaced PCB's, each in parallel relationship to the others, and each perpendicular to the backplane, has been adopted to implement complex electronic systems, this is not accomplished without limitations and problems.
Actually, a major limitation of this conventional structure is that, since the connectors are located on the edge of the PCB's, there is a stringent practical upper limit 125 to the number of interconnections that can be achieved between each PCB and the backplane while maintaining the size of these to reasonable dimensions and keeping PCB's and backplane form factors (i.e., width to length ratios) within manufacturable ratios. Moreover, as advances in microelectronics allow chips to increase in speed with additional I/O's, PCB's and connectors are required to pass these higher density signals at faster edge rates. Especially, telecommunications and networking designers have requirements for PCB to PCB interconnects to perform at sub-nanosecond rise times and with even higher signal densities than conventional products (such as a processor and its memories mentioned above). Thus, high performance sophisticated connectors must be used in these types of applications, requiring that signals be propagated on differential pairs with matched impedance and internal shielding to prevent signal cross-talk. Therefore, connector density becomes a constraint in such backplane system designs. State-of-the-art connectors are able to pass signals having sub-nanosecond rise times, e.g., rise times expressed in tenths of picoseconds. The two connections required by each single signal pair and the numerous ground connections needed to prevent cross-talk must be taken into consideration, to accommodate simultaneous switching and, generally speaking, to allow good signal propagation. Without increasing the size of backplanes and PCB's beyond a reasonable size, the number of signals that can span on the edge 125 of a PCB, plugged in a conventional backplane 130, must stay well below 1,000 since, over 12 inches (a reasonable size), a maximum of 500 to 840 signals can be handled according to the above stated connector density.
To stay current with an explosive demand for bandwidth, fueled by progresses in fiber and optoelectronic devices, such as DWDM (Dense Wavelength Division Multiplexing), the telecommunications and networking industries are developing network switches. These are mainly geared at allowing the deployment of a faster Internet that would meet the level of performance expected by mature business applications. Irrespective of the protocols in use (in practice, IP or Internet Protocol, tend to be the dominant protocol though), those products must be capable of sustaining the dispatching of traffic entering a network node through ingress ports, to appropriate egress ports, so that all types of individual communications are moved towards their final destination. One common platform in this industry is as shown in FIG. 1(b) and includes a single shelf 170 typically comprised of many, e.g., 16, port adapters 175 with a switch fabric in the center 180, thus following the traditional model hereinabove discussed. Because the carriers (e.g., the telephone companies, the service providers and the like) require the fabric to be fully redundant, there are both active and back-up switch cards 181 and 182, respectively. Port cards must typically be equipped today, each with optics at up to OC-192 (10 gigabits/sec.) to match the expected level of performance at a network node. Therefore, these feed 10 gigabits/sec. of IN and OUT traffic to both switch cards. Thus, as much as 16×10 gigabits/sec.×2=320 gigabits/sec. of switching bandwidth must be carried on the backplane, through the switch connectors to/from the port adapters. Moving hundreds of gigabits/sec. of bandwidth, and soon terabits, requires numerous high-speed serial lines to interconnect the components. Depending on the speed of these lines (each in the gigabits/sec. range), hundreds of such lines, if not thousands, are required on the backplane and through the connectors of the switch cards to meet the overall bandwidth requirement. Thus, exhausting or exceeding the I/O connection capability of the switch cards is possible when the number of ports to be implemented is higher than the one of this particular example (32×32 or 64×64 port switch are also common requirements) or if the port adapters must be upgraded to the next level of the optical carrier hierarchy, with four times faster optics, i.e., OC-768 at 40 gigabits/sec. Thus, when aggregate throughput has to be expressed in terabits/sec., the standard backplane solution of FIG. 1(b) just cannot accommodate the very large number of high speed serial I/O that are required to match the overall bandwidth of the switch core 180.